Gibson architecture
From JuniperClue
The Gibson architecture was initially designed for the T640, but has since been used in the T320 and M320 as well. It represents a departure from the flat shared memory model of the Martini architecture in that it utilizes multiple packet forwarding engines with their own buffering, interconnected by a crossbar (Clos in the case of multichassis) switching fabric. The Gibson architecture was designed to support improved port density and packet forwarding performance, and to support multichassis operation for very high scalability.
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Packet flow overview
Packets enter a Gibson router via PICs (type 1, type 2, or type 3 PICs are supported depending on FPC type); on the FPC the PFE segments the packets into J-cells, extracts a lookup key which it sends to the IP ASIC, and stores the cells in memory. The IP ASIC makes a routing decision and directs the cells to their egress PFE, where they are again stored in memory. A second route lookup is performed, and the cells are reassembled and directed to an outbound interface.
For example, a packet flow from interface 0/0/0 to 1/1/0:
Routing Engine (RE)
The Gibson architecture uses a routing engine just like the Martini architecture.
Packet Forwarding Engine (PFE)
Each FPC contains one (M320, T320) or two (T640) packet forwarding engines. The PFE, which consists of several custom ASICs and high speed memory, is the heart of the packet forwarding process.
The Gibson architecture uses several ASICs:
- L2/L3 Packet Processing ASIC
- Switch Interface ASIC (SI)
- Internet Processor ASIC (IP)
- Queuing and Memory ASIC (Q&M)
- Fabric ASIC
Several of these ASICs can operate in multiple modes, which enabled Juniper to use the same part in multiple places in their design.
Detailed PFE packet flow
An inbound packet first receives media specific handling on its ingress PIC. It is then passed to the L2/L3 ASIC which performs:
- Control information extraction (protocol type)
- Input accounting
- L2 header removal
- Segmentation into J-Cells (Jcell flows shown in blue below)
The L2/L3 ASIC passes the cells to a Switch interface ASIC operating in network mode. While in network mode, the SI ASIC performs:
- Routing lookup key extraction; the SI ASIC can be programmed to extract any needed information.
- Sprays the cells to the Q&M memory ASICs and collects the locations of the stored cells.
- Combines the locations, the lookup key, and interface information into a notification (shown in red below).
- Sends notification to the IP ASIC.
The IP ASIC used in the Gibson is a new design based on the IP2. It is able to perform 80 million packet forwarding operations per second. The ASIC uses the lookup key in the notification to determine the correct handling of the incoming packet. It then amends the notification with its routing decision, priority information, rewrite actions, etc, and passes the notification on to the Q&M ASIC in queue mode.
While in Queue mode, the Q&M ASIC:
- Queues notifications in 4 banks of DRAM (not shown in chart)
- Performs priority queuing
- Performs RED
- Polices and rate-shapes traffic
- Forwards a notification to the fabric mode of the switch interface ASIC when it is time to dequeue the packet
After receiving a notification, the switch interface ASIC in fabric mode performs:
- Fetches packet data from Q&M memory using the addresses in the notification
- Adds a header and CRC to each sell. The header contains the source and destination PFE, and a sequence number used to prevent cell reordering
- Sends and receives flow control across the fabric
- Transmits cells towards the fabric
The egress PFE performs the reverse of the same operations.
Switch Fabric
A switch fabric interconnects all the PFEs. The switch fabric consists of 4+1 'slices'. Cells are sprayed across the slices. With 4 slices operational a T640's fabric is nonblocking. The system can run with fewer slices operating but with degraded performance.
Flow control
- Requests
- Grants
