Calvin architecture

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Image:ABC-Chip.jpg
Juniper ABC-Chip ASIC

The Calvin architecture is a minimal respin of the Martini architecture created for the M7i (Codename: Calvin) and M10i (Codename: Hobbes). Its functionality is almost identical to Martini, the changes were primarily made to reduce costs.

The Martini architecture consists of several discrete ASICs: Two A-Chips, one B-Chip per FPC, and the CF-Chip. In Calvin these were combined into the ABC-Chip for a large cost reduction and lower power requirements.

Other changes include:

  • Improved silicon process.
  • Reduced board space.
  • Support for lower cost and denser external memory. including:
    • DDR SDRAM
    • ZBT SRAM
  • Only two banks of SRAM, rather than four.
    • This reduces lookup bandwidth, so the number of lookup processors in the CF were reduced as well.
    • As a result, ABC-Chip is only able to forward around 16Mpps vs CF-Chip's 40Mpps.
  • Only two banks of DDR SDRAM rather than four banks of EDO
    • Because of DDR, it provides the same bandwidth.
  • B-Chip component in ABC has double the microcode space from B-3.0.

The forwarding engine board, the CFEB, in Calvin architecture routers contains the entire PFE minus the PICs themselves. The CFEB used in the M7i and the M10i is the same part. Since the M7i only has four pic slots the second B-Chip is used to support the fixed PIC, on-board tunnel services, and the optional on board Adaptive Services module.

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